Friday, November 30, 2012

Impedance matching: An example

Impedance matching is a key task in RF design and and also in lower frequency design where power transfer is an issue. A number of techniques exist to do this. Some are built-in scripts for advanced CAD programs while other techniques are manual. One of the techniques used quite commonly is the L - Section impedance matching technique. It is of interest to examine this technique. A recent technical memorandum released by the techteam at Signal Processing Group Inc. describes in some detail the matching of an antenna impedance and a resonant circuit associated with the antenna. It shows the detailed development of the matching circuit and checks that can be made to evaluate it. A PSPICE simulation is also shown along with the .cir file and plots. Interested readers are directed to the SPG website at > "Engineer's Corner" for details.

Wednesday, October 17, 2012

The quarter wave matching transformer

In many high frequency applications matching a transmission line of known impedance to a known resistive load is an operation that is done over and over again. A simple way to do this is to use a quarter wave transformer. This concept is explained more fully in a paper released by Signal Processing Group Inc. recently. Interested readers may access this at the "engineer's corner" in the SPG website located at

Tuesday, October 16, 2012

Series to parallel conversion of LCR circuits

In a number of applications, specially in impedance matching LCR circuits may undergo series and parallel conversions. These conversions leave the performance of the circuit unchanged. They simply change the configurations to provide for a more appropriate architecture for the operation ( whatever that may be). A simple paper released by Signal Processing Group Inc. describes a method to do this. Interested parties may go to the website at and access the paper from the "Engineer's Corner".

Friday, September 28, 2012

IC design and reliability: Failure rate and the FIT

The failure rate for ICs is defined by: (Number of devices failed/Total number of devices tested)(1/time). The units can be stated as failures per device hour. This is an important parameter and has to be considered as early as possible in the design of the device. A unit called a FIT can also be defined. In this case a FIT = one failure per 1 billion device hours of operation. A FIT can be used to evaluate devices and distributions. The simplest model of failure is given by the parameter called the mean time to failure or MTTF. MTTF = 1/KF. Here KF is simply the failure rate per unit time. This is used in the exponential model which is very popular. The exponential model is simply expressed as: Fail(t) = 1.0 - exp(-KFt). This model is easy to use and calculate and can be used to assess the design of the device based on a failure rate model. Data is usually available from foundries for the use of this model. Please visit our website at for more ASIC and module design and manufacturing information. Please contact SPG for detailed information on more extended types of failure expressions and their use in the design of devices. i.e how these failure parameters mesh with design parameters that allow the design to be more robust in terms of MTTF or failure rate.

IC design and reliability issues

Reliability is a key issue with complex ASICs. Reliability data is important to the cost and long term performance assessment of the device and indirectly of the entire module, and ultimately to the system itself. The operating conditions that affect reliability are: (1) Temperature (2) Humidity (3) Temperature cycling (4) Voltage stresses (5) Current stresses. These stresses if applied with sufficient magnitude, will cause rapid deterioration and ultimate failure of the device. So it is only logical to use these stresses to evaluate reliability of the device. JEDEC stress testing standards are one way to come up with set of approaches to assess the reliability of the device. The website is

IC design for mini(TM)ASICs and macro(TM)ASICs.

We have divided the ASIC types that we develop into two categories. These are the miniASIC and the macroASIC. This nomenclature applies to the functionality, size, complexity, cost and risk of the device. A miniASIC is a device with very few elements on it. It is small in size ( remember size differentiation; 50 mils on a side is small, 100 mils on a side is medium and 250 mils+ on a side is large for analog, RF, wireless or mixed signal ASICs). Examples are: 2 power/high voltage MOSFETs, a closely matched high frequency differential stage, multiple bipolars or MOSFETs on a chip (used largely for bread-boarding and proof of concept sometimes. Although these can be valuable adjuncts to a board design in production as well.) A low logic gate device, more logic gates than a CD4000 series device perhaps, but less than a large digital design ( 5k gates+). Matched resistors, capacitors, inductors and interconnect on a chip. A macroASIC on the other hand lies at the other end of the spectrum. It is a larger device,(definition above), it is more complex and costs more. In our experience both types come in handy when developing systems. The miniASIC can be used as part of glue circuitry ( when the exact device you need is not available of the shelf and it has to be cheap). The macroASIC is the device of choice when you want to sweep many discrete components on to a piece of silicon ( or GaAS, SiGe, GAN, etc)to provide enhanced performance, reduction in cost, safety of R&D, increased reliability and manufacturability, testability, and so on. Signal Processing Group Inc., provides both types of devices. The only drawback is of course that you cannot just go out and buy something quickly off the shelf. Lead times for these ASICS is of the order of 2 to 10 weeks. However, if the planning takes this into account then mini and maro ASICs become a sound choice. Please visit our website at for more info.

Sunday, September 23, 2012

Image reject mixer: Description of operation

Image reject mixers are interesting circuits used in RF/wireless receivers to avoid the problems associated with the image frequency. ( To read about the image frequency please search for "image frequency" in this blog). A recent white paper from Signal Processing Group Inc, examines the operation of the image reject mixer and provides a fairly detailed explanation of the operation for interested readers. Please visit our website at > Engineer's corner

Saturday, September 22, 2012

Injection locking in transmitter chips

An interesting titbit of knowledge about direct conversion transmitters is the phenomenon of injection locking. If the transmitter is such that right after the modulation the signal goes to the driver/PA ( i.e there is no up-conversion or filtering of any kind between the PA and the modulator and its associated LO, then feedback from the output can cause ( in a number of cases) the LO frequency to shift and lock to another harmonic of a feedback signal. A number of techniques to alleviate this have been investigated because the direct conversion technique is considered by some to be simple and easy to handle ( keep chip size small). For more information or articles visit our website at

Dot rule for magnetically coupled circuits ( baluns and transformers)

In a magnetically coupled circuit like a balun or a transformer the phasing of currents and voltages is commonly indicated by the dot rule. Place a dot at either end of the primary. Drive this end positive ( for example). Measure the voltage at the secondary ends. The end of the secondary which is also positive ( or generally in phase ) with the primary end is also indicated by a dot. The other end of the secondary will be 180 degrees out of phase. Current flowing into the dotted terminal at the primary end will cause the current to flow out of the dotted end of the secondary and vice versa. Visit our website for more information and articles of interest at

VSWR control on chip

High levels of mismatch, for example in a transmitter or any output power device, can sometimes cause catastrophic failure of the device and its associated subsystem. Depending on the application this can be a severe problem. An interesting approach to prevent or control these types of failures is the use of an on chip integrated power detector. The power detector is used to estimate reflected power and if the VSWR (matching) gets really bad ( due to aging, component failure or other such causes) the power detector either signals a problem before it reaches irreversible levels, or executes automatic control of VSWR. Please visit our website at for other interesting articles or just information.

Saturday, September 15, 2012

High voltage IC design considerations

High voltage IC design is, in our opinion, an art. In terms of the implementation of the functions, simulations and layout it is a taxing endeavor. A number of fabrication vendors who offer high voltage technology try to make it as easy as they can, sometimes by providing some IP. In spite of this there are number of issues and challenges that come up, which the designer only learns through experience. When you are designing at voltages in the range of 500V to 700V and at high currents as well, it becomes a real challenge. It helps if the designer understands some of the parameters of the high voltage device, related to its operation. A white paper on this subject is available in the Signal Processing Group Inc., website located at in the engineer's corner. An old adage says " when you are working with high voltage and specially on the bench, keep your left hand in your pocket!"

Sunday, September 9, 2012

The 2-s complement number and DSP

More and more DSP ( digital signal processing) techniques are being used in most complex circuit designs including IC design. In general dsp requires the use of binary numbers. After all dsp is akin to a set of computations yielding a result which may or may not be converted into an analog signal. Both ways. At the input using an A/D and at the output using a D/A. In fact this is the way many recent designs in wireless are being implemented. The number system most often used is the 2-s complement number system. To refresh our memories, a 2-s complement number is formed by taking the binary representation of a decimal number, inverting the bits and then adding a "1" to it. This generates the 2-s complement. A wealth of articles exist on this in the literature and the web. The nice thing about the 2-s complement number is that addition and subtraction become very easy. An example is a dual modulus frequency divider. In this circuit we have two counters that start with a loaded number, an initial seed, and then this number is counted down. When the loaded number goes to zero a reset occurs. This is almost the very basic operation required in a dual modulus frequency divider. Note how easy the countdown becomes when implemented with 2-s complement numbers. Have the initial storage in a set of FFs, at each clock invert the contents of the FFs, use a simple adder, add 1 and at the falling edge of the clock recapture the results back into the storage FFs. Each time the clock occurs the FFs count down by '1'. Please visit the Signal Processing Group Inc., website located at http:/ for more information on our unique services, technology and technical articles. Contact us on this or other blog posts or articles as needed.

Saturday, September 8, 2012

IC Design primitive components available in typical semiconductor processes

When an engineer is in the process of designing a board level product, he or she instinctively starts a search for off the shelf components that are required to implement the architecture that the engineer has chosen to satisfy the requirements of the product. Yet in some cases a particular function in the architecture cannot be realized using an off - the - shelf component. At this point the engineer may decide that he/she needs a custom part, sometimes an ASIC. The question is what kinds of typical primitive devices can a semiconductor process provide so that the required ASIC can be implemented. A reasonable list of such components is given in for the interested reader. Please also visit for more information.

Tuesday, September 4, 2012

Integrated or chip antennas for RF microsystems

As the RF/wireless boards get smaller and smaller, as the active and passive device sizes shrink challenges of the antenna loom larger. Antennas may take up a large percentage of space. Even a few years ago PCB antennas were a solution but that is now no longer a very acceptable solution. The migration path for really small size antennas is the chip or integrated antenna. This tiny device becomes a practical solution when space is at a premium. A number of vendors have started offering this device and depending on the system parameters could be a pragmatic solution. Contact SPG at for further details or discussions.

Tuesday, August 28, 2012

Analog and mixed signal design: The level of simulation required for a first pass success.

What does the level of simulation have to be to predict the level of success of an IC? What does "level" imply? In the context of simulation of an IC, level implies how much of the IC was included in, perhaps a circuit simulation in a "SPICE-like" simulator. The reason this is so important is that in many cases it is not possible to simulate a full chip, specially if the chip contains mixed signal elements or large and small time constants, etc. Therefore the level of simulation for first pass success should be 100%. i.e the full chip was simulated under operating conditions that are a 100% identical to actual. It is of course not really possible to do this. It usually takes a combination of CAD tools to do this starting from MATLAB-SIMULINK, through circuit simulation and perhaps IBIS type modeling and simulation. In a few cases even more extensive simulation may be performed using Thermal Simulators. So the question remains:what is the level of simulation required for a high degree of confidence in the success of the chip? The answer must surely be that when all the CAD~tools have been used to their ultimate capacity, add a large measure of engineering judgment. This is the only way currently known! Please visit Signal Processing Group Inc.'s website at for more technical papers and information.

Monday, August 27, 2012

ASICs versus analog and RF/wireless ASIC

The term ASIC may be a misnomer for an analog or RF/wireless/MMIC device. When we think ASIC we seem to equate the term to a large digital chip done in very fine line technology costing many millions of dollars, taking a long time, fraught with risk and fear. That is an apt description of the large digital ASIC in our view. However, an analog or mixed signal or RF/Wireless/MMIC custom chip does not play in the same ball park or even in the same neighborhood. For starters these types of devices tend to be smaller and in terms of number of active devices less complex. Sometimes an analog or mixed signal or RF/wireless/MMIC device may only be a couple of devices! Perhaps its time to come up with a new buzzword for these types of devices. Please check out Signal Processing Group Inc website at for more information on these helpful devices. If you register you can get a userid and a password for protected areas of the site that contain much valuable information.

Wednesday, August 15, 2012

Manchester decoder and encoder

A final design of the manchester decoder and encoder was completed in record time. The encoder is of course, the simpler part ( or so they say). However, it turned out that when loopback was applied to the encoder decoder combination the source of malfunction in the initial iteration was traced to the so called easy part, the encoder. So designer beware, the decoder only seems more difficult. It is the encoder that will get the designer in trouble.There are few "nitty-gritties" that have to be addressed. For more on the subject contact Signal Processing Group Inc., at

Saturday, August 11, 2012

Analog IC design: The case for ASICs

Recently we had a conversation with a design engineer involved in the implementation of a wireless communication system. His input was interesting . He indicated that even though he got a majority of his devices right off the shelf, it turns out that he still had glaring gaps in his implementation . The reason for this, was that his application required some customization which could only be done using ASICs, both digital and analog. His initial solution to the digital problem was the use of programmable logic devices ( PLD). However the cost of the PLD in volume was prohibitive. So ultimately an ASIC was the only solution. Certain analog functions were also put into an ASIC for the same reasons. So the lesson is that although the design engineer can buy off the shelf devices for a majority of his design implementaion he cannot entirely fill his BOM with standard devcies and for the optimum solution may require one or two ASICs. Costs for ASICs can be made quite low. Please visit for more information about ASIC implementations.

Wednesday, August 8, 2012

4 Bit synchronous counter design revisited

Synchronous logic is usually preferred because everything gets synchronized to a clock and race conditions are generally avoided in design. A look at a 4 bit synchronous counter showcases the method quite clearly and may be of use to practitioners of the art as a refresher and to designers new to the field. A brief paper on the design of a 4 bit synchronous counter has been released by Signal Processing Group Inc., and may be found in the "Engineer's corner" at for interested users.

Tuesday, August 7, 2012

Manchester decoder

Manchester codes are a way to combine clock and data into a single stream and send it serially over a communications link, wireline or wireless. Manchester encoding is relatively simple and is basically a modulo-2 operation with the variables being the clock and data. The clock is actually twice the frequency of the original data clock. Care must be taken to make sure that there are no glitches or spikes in the resulting waveform. Manchester decoding on the other hand is much more involved and is not a trivial operation. There are a number of techniques to do this. Some are software based, some are hardware based. Some are based on time delays while others are based on PLL type circuits. The techteam at Signal Processing Group Inc., has analyzed a number of these techniques and come up some circuits that do Manchester decoding. Interested users may contact SPG at for details. A NDA may be required.

Sunday, August 5, 2012

EEPROM substitute for non volatile ID storage

After having struggled for a fairly significant amount of time to design a circuit to read EEPROMs for storage of IDs for a radio communication system, it suddenly hit us that we did not need to do this. Designing either a hardware circuit to use I2C based EEPROMs or a software equivalent is an experience that we think we would not like to have again if we can avoid it. From datasheets that the designers never have their own people use to involved and intricate operation ( WRITE, READ etc); its a nightmare. On the other hand we came up with a simple way to store IDs with almost trivial ease. Its as they say " a no brainer". For design engineers who are fed up with the EEPROM method, we say try this other technique and you will see how easy it is and how CHEAP it is! Contact us from the Signal Processing Group Inc.'s website at for a discussion. You may have to sign a NDA but if you are really serious then this should not be a show stopper.

Thursday, August 2, 2012

I2C interface and Manchester encoder chip

A fairly common operation in communications is the sending of an ID over a radio channel to establish a secure link. One method to do this could be to use a serial EEPROM ( 128 bits typically) with an I2C interface and a Manchester encoder. The receiver has a decoder which recovers the signal, clock and data. A chip that can do these types of functions would be a really useful device. Except that a search on the web failed to yield a product like this. One or two semiconductor companies have Manchester encode/decode devices but they are prohibitively expensive in addition to not having the needed I2C interface, serial shift register etc. etc.. A PLD could be used to do these functions except that in volume the PLDs may not be competitive. Signal Processing Group Inc., has developed an encoder and decoder for manchester code based communications. Please contact Signal Processing Group Inc., at for details.

Sunday, July 29, 2012

PLL ( Phase locked loop) design and simulation using Analog Devices freeware tool.

We have been looking at various RF/Microwave design freeware tools recently. One of the tools that we looked at closely is the Analog Device ADsimPLL tools. This allows the design of PLLs and synthesizers using AD's devices which come pre-programmed in the software. The tool is interactive and fairly intuitive and user friendly. There are of course, a few challenges but considering that one pays nothing for its use it is well worth the time spent on analyzing and using it. We designed a 1.83 Ghz loop using the AD4360-7 device. The tool allowed us to calculate the various PLL related component values and provided a quick assessment of the operation both visually and textually. We would have liked to see some additional small features in the tool but all in all our assessment of the tool is quite positive. For further information on this or on PLL design activity at SPG, please visit our website at and use the contact menu item for any further discussions or questions on our experience.

Sunday, July 22, 2012

Estimating the signal band noise in delta-sigma modulators

Sigma delta modulators are popular devices used in a multiplicity of applications. One of the most prolific of these is the A/D converter. A delta - sigma A/D basically consists of a delta-sigma modulator ( typically first or second order), followed by a decimation filter. The modulator operates in such a way that it generates a high pass response for the noise in the system. This response is known as the NTF or noise transfer function of the modulator. In this way the modulator suppresses noise within the passband but allows the out of band noise components to have a high pass characteristic. A low pass system of decimation filters removes this latter noise also. It becomes imporatnt,in the practical sense, to estimate noise in the passband. An expression can be developed to do this for higher order modulators with fairly accurate results. This subject is dealt with in a recent brief paper released by Signal Processing Group Inc. It may be found in> "engineer's corner".

Thursday, July 19, 2012

RF/Wireless design freeware

A survey using search of RF/Wireless/MMIC freeware on the web led to a nice harvest of freeware routines that provide useful tools for those of us who may want to use these types of programs. It is well known that a number of EDA companies sell fairly expensive RF/Wireless/MMIC programs. For many designers it may be difficult to buy these because of the cost. For these users the freeware that is available on the web might be a partial solution. The freeware programs are not as beautifully formatted but appear to be reasonably accurate when compared to results provided by the more expensive packages. An ongoing interest for us is to take a look at these freeware programs and assess their usefulness and price/performance ratio. A useful package distributed free by Agilent is the first on our list. It is called "appcad" and may be downloaded free. Apart from the marketing type information in this package a number of useful tools are included. It certainly deserves a close look.

Tuesday, July 17, 2012

SINAD: What is it and why is it important?

SINAD is figure of merit typically for radio receivers or similar devices. It may also be used in other applications. SINAD compares the signal power, the noise power and distortion power of signals. The specification is usually used in an audio sense. i.e the quantity under consideration is the quality of the received audio. A report on SINAD, its definition and other related parameters is available in the Signal Processing Group Inc., website at > engineer's corner for interested parties.

Logarithmic amplifiers ( LOG AMP): A very useful component.

Logarithmic amplifiers or Logamps as they are commonly called are very useful components. They are used in communications, RF and wireless systems, cell phone base stations, audio systems, and power control to name a few application areas.. A typical use in RF/wireless is in the RSSI ( received signal strength indicator) circuit. The logamp can be deceiving in its functionality so a basic description is of help for those who plan to use it. A paper on this component and its basics is available on the Signal Processing Group Inc. website under the "engineer's corner" menu item.

Thursday, July 12, 2012

Design considerations for integrated circuit RF/MMIC power amplifiers

Integrated circuit RF/MMIC power amplifiers are getting more and more popular. The PAs can be standalone or part of a larger device. Multiple technologies exist for the implementation of the circuits from CMOS to III-V. For the designer of these circuits different technologies present different challenges. In a brief paper by Signal Processing Group Inc., technical team, some of these issues are explored in a cookbook fashion. The paper may be found in the SPG website at>engineer's corner.

Sunday, July 8, 2012

What in the world are Hogenauer filters?

Hogenauer filters are sometimes better known as CIC filters. This begs the question: What on earth are CIC filters? CIC stands for "cascaded integrator-comb ". These filters are used very often as sigma - delta A/D decimation filters and the inverse ( interpolators ) are also used in image processing and other applications. These are examples of multirate filters.

Eugene B. Hogenauer published the principles of these filters in his paper entitled:
" An Economical Class of Digital Filters for Decimation and Interpolation", IEEE Transactions on Acoustics, Speech and Signal Processing, Vol ASSP-29, No. 2, April 1981.

These filters came to be known as Hogenauer filters. CIC is just another name for the structure he proposed. That I believe answers the fundamental question posed in the title of this post.

We decided to investigate these filters a little more in an attempt to demystify the mathematics and the structures so they would become more friendly to us practising engineers. In the attempt perhaps also come up with a few useful formulas or graphs or tricks for usage.

The result of this work is detailed in our wesbite at>engineering pages>hogenauer filters. Interested readers may peruse this interesting paper at their convenience.

Saturday, July 7, 2012

Analog and mixed signal design: Thermal management of device dissipation

More and more thermal management is required for current analog devices as power dissipation levels climb. In some devices such as power amplifiers, LED drivers, DC - DC converters and other higher power devices, the problem is so obvious as to sometimes burn one ( and not just metaphorically speaking) in a significant manner. The demonstration of the Dell laptop which burst into flame not so very long ago was a vivid demonstration of what we as design engineers have to live with. Its not just the power devices that need thermal management. A cooler device will run better in many environents so even lower power devices need thermal management. A PCB with various power level devices mounted on it needs thermal management. In spite of these reasons thermal management is not as well understood as one would expect. This post is an attempt to bring attention to, and provide some useful information for thermal management. In a recent report released by Signal Processing Group Inc, to be found at, information and resources can be found by interested parties. Please go>engineer's corner and access the thermal management articles.

Friday, July 6, 2012

Quadrature detection in FM

Quadrature detection of FM signals is a well known technique that has been used for a number of years. It uses phase shifting and multiplication of signals to detect FM modulation. A recent whitepaper by the techteam at Signal Processing Group Inc., describes this type of detection and presents an analysis for the more technically minded. The paper can be accessed at the "Engineer's Corner", in the SPG website located at

Monday, July 2, 2012

Image frequency in RF/wireless circuits

The image frequency in Rf/wireless receivers is an issue that has to be understood by radio designers and tackled for robust design. The image frequency is a so-called spurious signal which can cause a number of bad effects.Its origin lies in the mixing of multiple frequency signals in the receiver mixer. A paper released recently by Signal Processing Group Inc., describes this effect in simple terms so that an understanding of the effect may be obtained by interested designers. The paper can be accessed in the engineer's corner at

Sunday, July 1, 2012

Difference between, ASIC, an analog ASIC, a rf ic or a MMIC

There are a number terms that are used frequently to describe the various forms of semiconductor devices used in the industry. An ASIC is one of them. Other terms are rf ic/ wireless ic, an analog ASIC, a MMIC and so on. So what are the differences between these devices? Ultimately all of these devices are semiconductor integrated circuits, indicated by the ic ( or integrated circuit abbreviation). However there are some differences between the various forms of these integrated circuits that lead to the differing nomenclature. Generally if there is no descriptive abbreviation before or after the "ic", then an ASIC is considered to be a digital device consisting of logic gates, digital memories, microprocessors or microcontrollers and associated circuits all integrated on to a relatively large piece of silicon. An analog ASIC or an analog ic is usually made up of mostly analog circuitry such as amplifiers, comparators, A/D converters, D/A converters,operational amplifiers, analog comparators, voltage references, regulators, etc. A pure analog ASIC or ic operates in the analog domain. It is usually smaller in size than a typical digital ASIC. An rf ic is distinguished by integrated circuitry such as transmitters, receivers, PLLs, modulators, frequency multipliers, rf amplifers, rf power amplifiers, mixers, inductors, transformers, baluns etc. An rf ic also operates at higher frequencies ( typically up to 1 Ghz). A mmic is a monolithic microwave integrated circuit. It may have the same type of circuitry as an rf ic but the frequencies of operation are much higher that rf ics. Currently mmics may be found operating at frequencies in excess of a 100 Ghz. A further type of device referred to as a mixed signal ic has both analog and digital circuitry on it. Sometimes the digital ciruitry is dominant sometines the analog circuitry is dominant.

What is an ASIC? Why use it?

ASIC stands for "Application Specific Integrated Circuit". This means that an ASIC is designed to be used in very specific applications. Another term for it is "custom" chip. For ASICs a customer specifies certain requirements and specifications and the ASIC supplier then designs to those specifications and supplies the ASIC to the buyer. As such, ASIC has become a generic term. The usage of ASICs has become popular owing to a number of features that ASICs offer. First, the ASIC is usually very small. So it saves space on a board or enclosure that the customer may be using. In some cases there is no way out for the customer,but to use an ASIC. This may be the case, for instance for hearing aids, watches, cell phones. ( Although, strictly speaking a cell phone uses a lot of standard devices in addition to ASICs).An ASIC can be a great cost reduction tool.Insertion costs, discrete device costs, manufacturing costs and other associated costs csn be saved by using ASICs. An ASIC is a very useful tool when it comes to hiding intellectual property ( IP). Most of the circuitry is inside a very small package and can be made to be almost impossible to reverse engineer. Obviously a well designed ASIC can also increase reliabity significantly. No wires to come loose, nor connectors to fail etc. All in all an ASIC can be very useful indeed. To read more about designing an ASIC for yourself please see the article in this blog.

Tuesday, June 19, 2012

Metastability in Flip Flops and logic circuits

Many faults in digital circuit design, specially those using flip flops can be traced to the phenomenon of metastability. It is something that for a long time was not even recognized as an error source. However, a number of design engineers including the author of this article have personally experienced the tragedy of logic failure owing to metastability. In most instances the failure is hard to spot and can take its toll on the engineer trying to debug a malfunctioning logic circuit. Sometimes the problem is made even more catastrophic because the circuit may function quite well under certain conditions and fail under others. It can literally drive the design engineer up the wall! In analog and mixed signal design, whether it is a lower frequency circuit or a higher frequency circuit the causes and effects of metastability remain about the same. For those readers who may have experienced this and wish to investigate further, please review the paper on metastability in the "Engineer's Corner" in the Signal Processing Group Inc., website located at

Quadrature detection for FM signals

Quadrature detection of FM signals is a well known technique that has been used for a number of years. It uses phase shifting and multiplication of signals to detect FM modulation. A recent whitepaper by the techteam at Signal Processing Group Inc., describes this type of detection and presents an analysis for the more technically minded. The paper can be accessed at the "Engineer's Corner", in the SPG website located at

Sunday, June 17, 2012

The ISM band: A review of the essentials

In 1985 the Federal Communications Commission issued rules permitting “ intentional radiators” to use the “ Industrial, Scientific and Medical (ISM) Bands ( 902-928, 2400-2483.5, 5725-5850 Mhz) at power levels of up to one Watt without end-user licenses. Originally these bands had been reserved for unwanted, but unavoidable emissions from industrial and other processes, but they also supported a few ( often military) communications users. The new rules led to the development of a large number of consumer and professional products and is considered to be an important step towards the development of wireless computing or multimedia applications. Applications in the ISM band include, wireless LANs, short range links for advanced traveller systems ( electronic toll collection), garage door openers, home audio distribution, cordless phones, private point to point links, remote control, wireless telemetric systems ( e.g electrical power consumption monitoring) etc. Applications seem to be limited by the imagination rather than technology. A drawback of the ISM band is lack of any protection against interference. In particular microwave ovens limit the useful range of such communications devices. The techteam at Signal Processing Group Inc. recently released a brief whitepaper on the ISM band. Interested readers can find this under the "Engineer's Corner" menu item in the SPG website located at

Thursday, June 14, 2012

Analog and mixed signal design: Opamp offset voltage

The DC offset voltage of a differential amplifier is an important parameter for most opamp applications. It also impacts the CMRR of the opamp. In most cases for simple applications the offset voltage of a simple opamp may be perfectly satisfactory. 1 - 5 mV for bipolar designs , 20mV to a 100 mV for CMOS designs. However, when the application is more stringent, very much lower offset voltages are required. In this case special techniques to reduce the offset voltage of the differential amplifier are used. A recent brief article about DC offset voltages released by Signal Processing Group Inc., is available for review in the "Engineer's corner" located in the the SPG website at For further help please contact Signal Processing Group Inc., directly at

Saturday, June 9, 2012

Transmission line stubs and microwave distributed filters

As frequencies rise in MMIC or high frequency design ( board or chip) lumped elements cannot be used for implementing filters. In this case a technique that is useful is the use of transmission line stubs. The use of these stubs leads to microwave filters which are practical (with a few constraints). These types of filters and the methods of implementation are discussed in a recent release of a technical memorandum by the Techteam at Signal Processing Group Inc. Interested readers may access this article at , in the "Engineer's Corner".

PCB electrical and thermal parameters for design

PCB design is not only a science but also an art, as every PCB designer knows. However, the art of design is predicated by the science to a certain extent and in order to do a good job a designer has to know certain parametric effects of PCBs. A recent whitepaper released by Signal Processing Group Inc., offers a brief treatment of the first order electrical and thermal parameters for PCB design that can be useful in PCB design, both for understanding, as well as robustness of design. The paper can be accessed via the "Engineer's corner" menu item in the SPG website located at

How many times did Thomas Edison fail?

A light hearted post. Having read a number of books, both on Thomas Edison's life as well as motivational we have come to the conclusion that no one really knows how many times Edison failed before he got his first light bulb working. Here are the different numbers so far: 6000 times, 11000 times, 21000 times, 1000 times, 10000 times and an astronomical 56000 times!! Perhaps someone out there has other numbers they might want to share with us. We can be contacted on our email at:

Thursday, June 7, 2012

Analog design entrepreneurs alert

This post is not engineering-centric.It is addressed to engineers who may have the entrepreneurial bug. Times have changed so much that there are new opportunities for people who have a developed product and want to profit by their efforts with little or no money expended. The online/cyber world has had a tremendous impact that could not be imaginged only a decade ago. Then an engineer with a product had very few avenues open to him/her to gain from it financially . Today there are a myriad of ways that can be done. For more information about these techniques please contact Signal Processing Group Inc., via the "Contact" menu item in the website located at

Sunday, May 27, 2012

Ground loops in analog and wireless design

Ground loops are parasitic paths in a PCB or an IC that can cause a number of bad effects. These are caused primarily by bad layout, circuit design or interconnections either accidentally or because of lack of experience. In order to avoid ground loops one has to understand what they are. A very brief description is given in a recent article by the techteam at Signal Processing Group Inc., and is available for review at their "engineering pages" in the website located at

Sunday, May 13, 2012

Ultra low power ASIC design

Power has become a limiting factor in many applications. Specially in portable products, wireless applications and temperature limited products and systems. Therefore it is useful to investigate and develop really low power, "ultra" low power devices ( Integrated circuits and modules) that can be used to build more complex systems. techniques such as low voltage devices, sub-threshold CMOS circuits, energy harvesting etc. all play a part in the design of such devices. It is a fascinating area of design. Over the past few years the techteam at Signal Processing Group Inc, has been involved in the design of low power circuits for use in RFID and 1.2V battery powered systems. Some of this work is available for discussion. For details or for help in the design of these type of devices please contact SPG at

Saturday, May 12, 2012

Silicon nitride, the "other" dielectric material

Silicon nitride is used in integrated circuits wherever a high dielectric material is required. We are most used to silicon dioxide as the dielectric used in IC fabrication. Silicon nitride has some properies that makes it a better dielectric sometimes. One of the chief ones is its use in the fabrication of higher value on chip capacitance. Its dielectric constant is approximately twice that of silicon dioxide. So a sandwich capacitor made using nitride will be twice as large in the same area as it would be if oxide was used. Common properties of nitride are listed in a table located at

Thursday, May 10, 2012

Accuracy of schematics of older analog ICs

It is an interesting fact that if datasheets of older ( 70's - 80's)devices are examined then then it will be found that the datasheet usually includes a detailed device level datasheet. This is more of a case with analog chips. Large analog device manufacturers have been more than generous in providing these with the datasheet as a guide for designers. The issue is though if the schematic is compared to the actual layout ( for example by taking a photo of the die) then many, many discrepancies will be found. This can lead to some very interesting errors in the design of the product with really no help from manufacturer as to why an effect may be seen to happen. In the case of the uA741 for example there are at least two or three different datasheet schematics available. Neither of them are accurate. So user beware. For more information on this topic please contact Signal Processing Group Inc, via their website at

Tuesday, May 8, 2012

A case study of a successful analog and mixed signal ASIC project

Although much has been written about the ASIC business model. It is still useful to study a real ASIC project in terms of the interactions of supplier and customer, timelines and the typical path from concept to a successful implementation, that allowed the customer to actually put his product into the market. ASIC development can be a very exciting and pleasant activity if certain methodology is followed by both parties, the supplier and customer. A case study that was released recently by SPG allows potential participants to get a feel, at a high level, of a successful ASIC project. The document may be accessed from the SPG website located at It can be found under the menu item " Engineer's Corner"

Sunday, May 6, 2012

Multipath wireless solutions: The RAKE receiver

Multipath in wireless systems is what happens when a transmitted signal travels along multiple paths ( e.g. as a result of reflections from surfaces). At the receiver these received signals can add or subtract depending on the amplitude and phase of the signals causing what is known as frequency selective fading. Another name for multipath interference. Obviously this is a real problem for cellular systems and many different types of solutions have been proposed and are being used. One of these solutions is the so-called RAKE receiver. The RAKE receiver has a number of "sub-receivers" called fingers, each assigned to a different multipath component. Each finger independently receives a single multipath signal. Subsequently, the contribution of all fingers are combined in order to make the most use of the different transmission characteristics of each transmission path. The important parameters that need to be estimated as accurately as possible are, the time of arrival of each finger signal, its amplitude and phase. Knowing these, the signals are combined in what is known as a maximal ratio combiner or a MRC. In this combiner each individual finger signal is weighted by the complex valued channel gain. The effect of this weighting is to compensate for the phase shifts in the channel and the change in amplitude. As this is done successfully significant improvement in signal reception is obtained. For details on a RAKE receiver design please contact Signal Processing Group Inc., through the website located at

Tuesday, May 1, 2012

A simple, silicon proven BiCMOS volage reference

Voltage references are ubiquitous components of analog design. The specifications of references vary depending on the application they are used in, from ultra accurate to simple. In most cases a simple voltage reference that is guaranteed to start up and provide a relatively accurate and stable reference voltage over temperature and power supply voltage is all that is necessary. Trimming is another task that can become complicated for references. However a simple voltage reference application may not even require that. In a recent free report released by the Techteam at Signal Processing Group Inc., a simple silicon proven voltage reference is presented It can be used as is, or if necessary can form a core cell for a more involved design. The report can be accessed at This design is available for implementation in a FASTCHIP project if needed.

Monday, April 30, 2012

Analog ASICs: Low cost, low risk, quick turn?

In the world of analog asic design, development and manufacture there are certain trade-offs that are conventional. You can have a low risk design, if you spend a little extra time on the design, you can do a quick turn asic if you are willing to assume a little higher risk and so on. Signal Processing Group Inc, has a technique called the FastChip which allows one to approach the three parameters of design relatively closely for smaller analog chips. The description of the technique is provided in the engineering pages on the SPG website located at Both low and high frequency designs can be accommodated. Interested parties can contact SPG for a list of the types of silicon proven designs available for immediate implementation ( or one can specify what one needs). To provide a frame of reference for performance parameters the following is provided as an estimator: Supply voltage ranges [1.2V to 550V), currents[<10A], frequencies[ DC to < 100 Ghz operating]. To get information on the types of quick turn silicon proven designs available as well as hard numbers on investment, timelines, etc please contact SPG through the website.

Monday, April 23, 2012

Lateral pnp current gain calculation

When a standard bipolar process is used in which there are vertical NPN transistors and lateral pnp transistors it is sometimes difficult to assess the lateral PNP parameters. This post addresses a way to estimate the current gain (BETA)of a lateral PNP from its geometry. The paper which describes this technique is located in the Signal Processing Group Inc., website at Interested readers are invited to peruse this article at their convenience.

Wednesday, April 18, 2012

Noise cancellation: The lock in amplifier

Noise cancellation in systems with low amplitude input signals embedded in large noise levels is always a problem. Few techniques are available to extract these low level signals from noise but tend to be expensive in many ways. Lock-in amplifiers can be used to measure very small AC signals(a few nanovolts).

The basic technique used by lock in amplifiers is known as phase-sensitive detection to single out the component of the signal at a particular reference frequency and phase. i.e. it is a very narrow band filter equivalent and noise signals are attenuated. For example. The signal is a 10 nV sine wave at 10 kHz. Amplification is used to bring the signal above the noise. A good low-noise amplifier will have about 5 nV/√Hz of input noise. If the amplifier bandwidth is 100 kHz and the gain is 1000, the output will be 10 µV of signal (10 nV × 1000) and the noise will be 1.6mv. This means it will be very difficult if not impossible to measure the signal of interest.

If the amplifier is followed by a narrow band filter, with a Q=100 centered at 10 kHz, any signal in a 100 Hz bandwidth will be detected (10kHz/Q). The noise in the filter pass band will be 50 µV (5 nV/√Hz ×√100 Hz × 1000), and the signal will still be 10 µV. However, the output noise is still much larger than the signal, and a measurement can not be made.

If the amplifier is followed by a phase-sensitive detector, then the PSD can detect with an extremely narrow bandwidth of 0.01 Hz! In this case the noise in the detection bandwidth drops to 0.5 µV (5 nV/√Hz ×√.01 Hz × 1000), but the signal stays at 10 µV. The S/N is now 20, and the signal can be measured.

Creative circuit design can be used to measure small signals in other parts of the signal spectrum also. The interested reader is referred to Signal Processing Group Inc ( website for more information. Please contact the SPG techteam through the "contact" menu item if needed.

Interestingly enough a monolithic version of the lock in amplifier is available with a 100dB range at a reasonable cost.

Monday, April 2, 2012

Analog and mixed signal chip/asic markets: A 2012 snapshot

This is not about engineering. Its about an equally interesting and relevant subject. A team from SPG took a look at what the various marketing and sales gurus are saying about the analog chip, and analog asic and mixed signal,market. A number of summaries(with credit to the references) has been included in the engineer's corner in the SPG website at Interested readers are welcome to read it. Any comments would be very welcome, especially as marketing and sales numbers can be somewhat confusing and "flexible". Some backbone could be inserted by readers who are in the forefront of the fray. Any comments will of course be available right here in the blog. Thanks in advance to those who send in their own comments and numbers so all of us can benefit. For more detail please access the detailed market reports ( at a serious cost by the way from the research companies)from the websites of the various references quoted right up front.

Wednesday, March 28, 2012

Noise in oscillators

Oscillators are very important components of any electronic system, be it in communications, signal processing, data acquisition or power electronics. In short, one always bumps up against oscillators in electronic design. Among other things that an engineer faces when designing oscillators or VCOs is the problem of ever present noise. It becomes important to understand the basics of noise sources and quantities in oscillators. Recently Signal Processing Group Inc., released an interesting paper on just this very subject. The paper may be accessed from the SPG website at under the engineer's corner menu item.

Thursday, March 1, 2012

Analog and mixed signal design:Medical device classification

Thinking of getting involved in medical device ASICs or products? Need to be aware of the classification methods used by the FDA. Over the years the regulations seem to have changed.There is good news and there is bad news. In order to get the scoop from the "horses mouth" a good link is as shown below. The simplest classification from the point of view of the marketing of a medical device is Class I. Class II follows close behind with the 510(k) authorization to aim for. The hardest and the most complex classification is Class III. Need time and deep pockets for this type of device development and marketing! Most people will stay away from this. The following link should be helpful and is the place to start if thinking about entering the medical device market in the US.

Friday, February 17, 2012

Analog and mixed signal design: Multi-die designs in a package.

As the levels of integration of integrated devices increase, engineers are looking for newer and unique ways to increase the levels of integration at low risk and cost. If the subsystem design to be integrated has widely varying performance, i.e high and low voltages, high and low currents, high and low frequencies etc. then it is not possible to use a single technology to integrate the device. In this case a multidie approach in a package is the best approach. In this technique chips with varying performance are put inside a package and interconnected. The die are fully isolated from each other so the interaction between them is assumed to be minimal ( or designed to be minimal). So an overall subsystem can be integrated inside a package. The advantages here are that a long and costly process of custom chip design can be avoided and varying specifications implemented. In recent years SPG has been doing this type of integration with success. Anyone with interest in this technique is invited to contact SPG through the website located at

Quick turn analog ICs with low risk : The SPG Fastchip technique

It is not unusual that the trio of risk factors: cost, timeline and performance are the inhibitors of analog and mixed ASIC usage. Techniques that can lower these risks can and should be used. The lowest order of risk reduction techniques is breadboarding. Using discrete devices to verify a circuit. However, there are a number drawbacks to this. First of all, a breadboard has higher parasitics ( capacitance, inductance and resistance) and when the design is transferred to an ASIC, performance may not match that obtained on a breadboard. Secondly it is not always that one can get discrete devices which are appropriate for the ASIC design. There are other factors of minor importance that also affect the mapping of a breadboard design to an ASIC. What is needed is a method to cheaply and quickly check out either part or all of a envisaged ASIC cheaply. The SPG Fastchip technique is one approach that is available from Signal Processing Group Inc. Its description may be found under "Engineer's corner" in our website at:

Saturday, February 11, 2012

Reverse engineering obsolete devices

In our work on resurrecting really old and obsolete devices using bipolar technology, some designed using rubylith techniques, we found an interesting evolutionary trend from the oldest to the older. The layout techniques and the basic designs were dictated by the availablity of or non-availability of CAD tools. The earliest designs tend to have the very simplest layouts for the individual devices such as: simple epi-tub, base and emitter rectangular diffusions. Large contact areas of every shape and description and very broad isolation and device to device spacings starting at almost 10 mils and coming down to about a mil for the older devices. Devices are layed out almost as one would layout a PCB using discrete devices. Active devices occupy their own tubs, resistors occupy their tubs and there is a general absence of capacitors. For the relatively newer obsolete devices the layout style changes to active devices, resistors sometimes occupying a single tub with very unique shapes and geometries. As the the CAD tools become better, circular geometries become more and more prevalent and we see lateral pnps and smaller npns with circular emitters. On chip capacitors make their appearance using the emitter diffusion, oxide /nitride and metal sandwiches. The line widths shrink down to sub mil sizes and device densities per chip increase. Interestingly bondpad sizes seem to be consistent for a long period of time ( around 100 um X 100 um). Scribe lines appear to also hold on to widths. ( Around 100 to 150 um wide). All in all the art of reverse engineering these devices, including the electrical characteristics as deduced from the layout and ancient specifications form a most interesting activity for those interested in the art. Interested parties may contact SPG for reverse engineering of obsolete parts via our website at

Learning from failures

This year SPG will be over 24 years old. We have had a long history of projects, most of which were great successes. A few of them spectacular failures. After much soul searching we decided to publish what we think were some outstanding reasons for the failures. As is understandable and usual there were shortcomings and challenges on both sides. SPG and the customer. This post tries to list these and should be read with respect to one of the earliest posts about first pass success, already published in this blog. The reason for this baring of skeletons is to help establish a better and better methodology for success and to avoid mistakes of the past. It may be slightly controversial but its veracity is unquestionable.

Project # 1.0 ( Non - chip project)
1.0 Communication problems. Customer and SPG not communicating comfortably and well.
2.0 No statement of work. No plan. No list of things to do and a timeline associated with it.
3.0 No clear guidance from the customer.
4.0 Bad, bad, bad documentation from the customer. Bits and pieces strung together in random order. Failure of SPG to not accept this.
5.0 Micro – managing by the customer instead of managing.
6.0 Too much anxiety on the customer’s part about the project.
7.0 No specification.

Project #2
1.0 Change of specifications and mission creep.
2.0 Failure to do full chip simulations.
3.0 Initial time estimates were off. Too aggressive a schedule.
4.0 Delay in implementation. Faults on both sides.

Project #3
1.0 Change of specifications. Mission creep.
2.0 Customer pushing to get the database out too quickly before checking got done.
3.0 Severe micro-management by customer..
4.0 Did not correct DRC or LVS problems completely because of 2.0
5.0 Lack of pcb expertise on the customers part.
6.0 Would not let us do the reference pcb design and initial test.

Project #4
1.0 Lack of right design tools and training to use them
2.0 Lack of good communication and comfortable give and take between the two parties.
3.0 Lack of appropriate effort on the project.

Project #5

1.0 Lack of the right process technology.
2.0 Used a process that did not have comfortable performance margins.
3.0 Circuit failure under stress conditions.

Saturday, January 28, 2012

Path loss in free space and received voltage at an antenna

Radio signals suffer a path loss in free space ( as well as in other media). Recently a brief article was released by SPG technical staff which provides some simple expressions for the calculation of this free space path loss These expressions are useful in quick calculations of received power at a close in distance for an antenna. Using these expressions, and the formula for calculating the induced voltage in an antenna as a result of the received power, is a starting point for more sophisticated calculations. This paper can be found at >> engineer's corner.

Monday, January 16, 2012

Super-Beta or high current gain npn transistors

In certain analog ICs it is necessary to have very high input impedance and very low base currents. For such applications, the typical current gains of an integrated npn transistor are not high enough. It is possible to increase the current gain of an npn transistor significantly by improving the base transport efficiency. In this case the base is very narrow ( a few hundred angstroms or less). The collector to emitter breakdown of a structure like this is relatively low ( 2V - 3V) because the collector base depletion layer can punch through the active base region into the emitter. This is the punch-through or "super-beta" transistor. Current gains of 5000 are obtainable using this technique at currents of 20uA or so with a Vce of around 0.5V. The fabrication of super-beta transistors in a standard process can be done by using one extra masking step and diffusion. After the base diffusion for the normal NPN transistors a special mask is used to open up the emitter diffusion for the super-beta transistors. At this stage the emitter of the super-beta transistor is only partially diffused.This step is then followed by the masking and n+ diffusion of the standard npn. Owing to the extra diffusion step for the super-beta transistor, the emitter of the super-beta transistor is diffused slightly deeper
than the normal npn resulting in a narrow base width.

Sunday, January 15, 2012

1.2V battery to 3.3V and 5.0V output power pcb design

Recent needs in low power and single battery ( 1.2V) design demand a power converter circuit. A recent requirement for a handheld FM receiver ( multichannel) necessitated
the design of a voltage supply converter using off the shelf devices. After a thorough search for off the shelf devices which could be used to realize such a converter a device was chosen from a popular manufacturer and the design was started. Here are some issues that we encountered, ( perhaps not new, but nonetheless need to be mentioned). Our biggest challenges, suprizingly enough had very little to do with the IC that we used. This was because the vendor had excellent technical support and application notes and had a well organized technical support environment. Our requests were handled within a 24 to 48 hour turnaround. The challenges that were difficult had to do with selecting, acquiring and using the passive components. These were harder to find and technical support left much to be desired. In spite of these issues we managed to finish the design in time and test the board. It worked quite well and provided 3.3V at close to 1.0A and 5.0V at close to 0.5A as needed with a 20% margin. Interested readers are invited to contact us through our website at

Tuesday, January 3, 2012

Wireless monitoring for animal health.

A visit to Germany and Switzerland was fruitful with some interesting ways the Europeans are using wireless technology. As elsewhere, wireless is being used in almost every restaurant to bill smart cards and credit cards tableside. An interesting application of wireless was encountered in the dairy farming industry where the use of wireless enabled bolus' monitor health and various other states of cows and other farm animals. This is different from RFID that is used in identification. An interesting aside to this is the fact that there is very little data available on the propagation loss of a radio signal through living tissue ( in bovines and other species). Frequencies are not really standardized. There is a European standard but it appears that vendors are still using their own specifications. Happy new year to all!