Sunday, October 27, 2013
When designing RF power amplifiers with active devices, it is always good to ask what the device is capable of in terms of power gain when everything is matched. i.e If I matched everything what is the maximum gain / performance I could get out of the device. The answer to this question lies in determining the MAG or Maximum Available Gain of the device. Of course, this is a theoretical quantity because it is not possible to get this performance in practice. The MAG then,is the theoretical power gain of a device when its reverse transfer characteristic or admittance/impedance is set to be non existent. In addition, its input and output ports must be conjugate matched with the source and load impedance respectively.Contact Signal Processing Group Inc., for all your RF Power Amplifier questons or needs. Please review RF power amplifier fundamental concepts at http://www.signalpro.biz/rfpa.pdf
Tuesday, October 22, 2013
Baluns are used quite extensively in electronic design specially in higher frequency or differential circuits. The term "Balun" is an abbreviation for Balanced - Unbalanced. The implication is that a balun converts an unbalanced signal to balanced signals. In some ways Balun operation is not intuitive. An article describing the basics of baluns is presented by Signal Processing Group Inc.'s technical team and can be accessed at http://www.signalpro.biz/free_report_form_balun.html
Saturday, October 19, 2013
FM signals are everywhere in the RF/Wireless world. Their resistance to noise and clean reception within their range of operation is exploited by many systems. It is useful sometimes to take a look at the theory behind these signals, at least to the point that an intuitive understanding can become beneficial. A recent paper by Signal Processing Group Inc., has been published that provides a description of the mathematics behind FM signals. A set of simulation results are provided that back up the theory. The paper can be accessed at the SPG website, http://www.signalpro.biz under " free stuff...".
Wednesday, October 2, 2013
Here are a number of reasons why you would want to develop your own ASIC or custom module, analog, RF or mixed signal. (1) You have developed a product using standard off the shelf components. When you did this your suppliers and their salepersons were all over you. Then the salesperson you knew left, or some other event took place. You no longer have the support from your supplier or distributor. Your project is stalled. Or even worse you have your product in the market and your supplier decides to discontinue the product you are using. The product is selling well. At this point you must have your own ASIC or module if you are to be independent of your supplier and their vicissitudes. It may take time and money but if market and product can support it, you must consider your own custom devices. (2) You have developed your product using off the shelf components. It is selling well. If the market is there and your product addresses the market, be assured your product will be copied and released to your market. You then have a number of choices. (A) Sue 'em. (B) Enhance your product. (C) Protect your IP (D) Exit the market. Only (C) is a palatable choice. You can do this by (E) Patents and trademarks (F) Hide your IP using full custom ASICs and modules (G) Enclose your product in a strong coating of some substance that is difficult to penetrate. Of these options we advocate full custom devices, ASICs or modules. You own the IP here, not your suppliers; It is very expensive to reverse engineer an ASIC and with the proper IP protection techniques ( coatings and other processes) it can be very difficult for a copycat to steal the IP. In addition if a portion of the IP is in firmware then this is an additional layer of protection. (3) Your product has been developed to the point of a demo model and it works. The boards and boxes are large and ungainly. You now have to fit it all in a really small area or enclosure. Again this is a really good reason to make your own custom ASIC or module. (4) Your product has been developed to the point of a demo model. It works fine except that it dissipates a lot of power. Perhaps it is a mobile unit and the batteries are running down. Whatever the case, this again is a really good rationale to get your own custom device. Custom devices can be designed to dissipate very little power using good low power techniques. (5) You have developed a product using discrete off the shelf devices. There are a lot of components on the board. This is causing a size increase and a manufacturing headache. Again use of a custom device is strongly recommended. Not only will the size and power come down but the overall product will be more reliable and easy to manufacture. If you want to learn more or develop your custom devices, please contact Signal Processing Group Inc, at http://www.signalpro.biz for a no obligation discussion or quotation. SPG uses state of the art semiconductor, PCB and assembly techniques to provide highly cost effective devices that belong to you.
Tuesday, September 24, 2013
A set of measured data were evaluated to establish some design targets for a USB3 front end circuit. This type of cable data is difficult to come by on the web so a TDR was used to measure two different length USB3 cables for only the loss characteristics. The measured data was bolstered by measured data from a USB3 cable manufacturer. The results are: 1 Meter long USB3 cable has a -3dB point at 5 Ghz. A 3 meter cable has its -3 dB point at 2.0 Ghz. A 2 meter USb3 cable has its -3 dB point at 1.6 Ghz.
PCB small loop antenna design is required when designing with RF transmitter and receiver chips available as standard parts from a number of semiconductor manufacturers. A web survey turned up a small number of interesting and instructive articles on this topic. Of these articles only a very few met our purpose. Among these latter we found the most useful to be the one presented by Microchip Technology, Chandler, Arizona. ( Jan Van Niekirk, AN831). We generated an EXCEL spreadsheet using this article as a template for designing these types of antennas. It must be mentioned that this spreadsheet ( as well as the information in the article was found to be a starting point for the design. Some tweaking is still required using measurements.)This spreadsheet is available for download by interested parties from the SPG website located at http://www.signalpro.biz under Free Stuff.
Monday, August 5, 2013
Now and then we come up against expressions in the design of circuits and systems that involve the use of complex numbers under the radical sign. When this happens it turns out that the whole technique is quite complicated and may involve De Moivre's theorem and polar form of complex numbers. Other techniques can be even more involved. Best of luck to the modelers who may be using these techniques. We found them at least as interesting as Bessels functions!
Saturday, August 3, 2013
Looking at the issue of the IEEE Journal of Solid State Circuits, after the 2012 Custom IC conference, with a critical eye for analog and RF content, the following interesting articles were found. A 3W class-D ampliﬁer with improved linearity was described that reduces external ﬁltering required for EMI protection by controlling the slew rate of the driver ampliﬁer and digital modulation to spread the PWM common mode signal to place a null at the victim channel. The 110 nm CMOS design achieves SNR of 95 dB at 85% efficiency. A second article describes a 2.3 mW 10-bit 170 MS/s ADC in 65 nm CMOS using a two-step binary-search assisted time-interleaved SAR architecture. The third article , presents a continuous-time sigma-delta ADC with a switched-capacitor return-to-zero DAC that helps to reduce sensitivity to clock jitter and improves linearity. The prototype ADC was designed in a 180 nm process. It achieves an SNDR of 82.3 dB for a 2 MHz bandwidth while consuming 16.5 mW and reduces clock jitter sensitivity by 28 dB. An interesting article describes comprehensive design considerations for interleaved ADCs and proposes a background timing mismatch calibration technique to reduce the image to 75 dB for input frequencies more than 500 MHz. Another article presents a 40 nm 2.1 GS/s 2x time-interleaved pipeline ADC tthat uses a digital MDAC equalization techniques using FIR ﬁlters. The 12-bit design achieves SNDR of 52 dB while consuming 240 mW. In terms of topics in RF design some interesting articles described various RF techniques such as: A digital PLL that uses a coarse/ﬁne TDC. The ﬁne TDC is implemented using stochastic techniques to achieve an overall TDC resolution of 4 ps. The concept is demonstrated in a 130 nm 1.99–2.5 GHz PLL with 213 fs rms integrated jitter. The next paper in this series describes dynamic latches, where the regenerative cross-coupled pair is removed for maximum speed, demonstrated in prototypes of divide-by-4 circuits in 32 nm CMOS operated between 14 GHz and 70 GHz. A switched-triple-shielded transformer technique to realize a wideband CMOS VCO that can tune from 57.5 GHz to 90.1 GHz was also presented. An interesting paper provided reviews of techniques for improved harmonic reject mixers using clock gating that allow better than 52 dB rejection for 3rd/5th/7th LO harmonics without any calibration. This should be of interest to front end designers. There were papers on wireline topics as well. A paper presented a reference-less CDR for SONET transceivers that uses an algorithmic frequency acquisition without using a training sequence. The concept was demonstrated on a 65 nm transceiver that achieves 400s acquisition time and a jitter tolerance of 0.5 UI for 10 mVppd( differential) input sensitivity. Another paper on the wireline topics describes a 20 mW 6b 1.6 GS/s ADC with embedded partial equalization using a 1-tap DFE for serial receivers. The prototype receiver is demonstrated at 1.6 GS/s over 46-inch FR4 link with 14 dB loss while achieving a 0.2 UI timing margin. The next paper presented a 10 Gb/s 2-tap reconﬁgurable pre-emphasis transmitter that consumes 10 mW in a 65 nm LP CMOS. Power management was not ignored and papers described advances in power management techniques especially for SoC applications. An interesting paper for an adaptive all-digital ripple mitigation technique for fully integrated capacitive DC-DC converters was presented. Coarse ripple control was achieved by varying the size of the bucket capacitance, and ﬁne control by time modulation of the charge/discharge charge transfer capacitors. The 130 nm design presented achieved 3x ripple reduction, 70% efficiency, and 24.5 mW/mm maximum power density. A power management unit was presented with a reconﬁgurable switched-capacitor converter in 65 nm CMOS to reduce the energy cost with sleep-to-active and active-to-sleep transitions by 64%. This energy reduction comes at small area overhead (lower than 1%) and no penalty in active mode. Another paper in the power management category presented a 190 nm CMOS, 87% efficiency, 0.75 mm on-chip feed-forward single inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation with 0.5 V startup. Its interesting to see that high voltage technology, techniques and circuits were glaringly missing from the issue that was based on the proceedings of the 2012 Custom Integrated Circuits Conference. There was a preponderance of papers utilizing analog technology ( and RF). Digital type technology was described but not in a large number of papers.
Friday, July 5, 2013
The voltage standing wave ratio and the return loss ( and its related quantity, the reflection coefficient)are all related to each other. Once any one of these can be calculated, measured or simulated the others can be derived. These quantities become specially important in the case of matching network design ( as in Rf Power amplifiers for example). A brief paper by the technical team at Signal Processing Group Inc., describes this. The paper may be found at
http://www.signalpro.biz > Engineering pages by interested readers.
Tuesday, July 2, 2013
RF power amplifiers come in multiple classes. A, B, C, D, E,F etc. Some of these are highly efficient but more non-linear. The Class A amplifier for example is very linear in operation but dissipates a lot of DC power. In order to understand the advantages and disadvantages of each, it is useful to study the characteristics of these types of amplifiers. An interesting paper was found in the literature which in our opinion is a good one for the student of RF amplifier classes. The reference is provided below for interested parties. " RF Power Amplifiers, Classes A through S -- how they operate, and when to use each". By, Sokal, N.O. Design Automation, Lexington, MA, USA. Published in the Electronics Industries Forum of New England, 1997, Professional Program Proceedings, Boston, MA. 6 -8 May, 997. pp 179-252.
Thursday, June 13, 2013
A technique used in the design of common emitter amplifiers, both to increase input impedance and bandwidth, is emitter degeneration. This consists of inserting an unbypassed series resistor from the emitter of the bipolar to a common point ( ground, virtual ground, etc.) The impact of this method on the circuit performance is explored in a recent brief publication by Signal Processing Group Inc. The paper may be found at http://www.signalpro.biz>Engineer's corner.
Saturday, May 18, 2013
L-Section impedance matching is a popular and simple technique. The basic principle is a single ended input to a single ended output. However, if one has differential inputs and outputs, a way has to be found to convert the single ended matching configuration to a differential configuration. A recent brief paper by Signal Processing Group Inc., addresses this issue. It can be accessed by interested parties at http://www.signalpro.biz >Engineer's corner.
Saturday, May 4, 2013
This brief note is an addendum to an earlier post on a low voltage modified Gilbert cell mixer. If the power supplies ( VCC ) do not vary too much ( typically 5%), then the low voltage mixer can be used as is. However, if the power supply variation is greater ( say 3.0 to 6.0V ), then the earlier design's current dissipation will be uncontrollable. In such a case it is best to revert to the standard Gilbert cell mixer. The saving grace is, that if the design is being done in a Bi-CMOS process, then instead of using a bipolar as the tail current in the mixer, a MOSFET can be used. Note that in this case the drain to source voltage of the MOSFET can be very low ( VDS=0.1V or lower) depending on size. In this case the power supply voltage will have a minimal effect on the performance.
Thursday, May 2, 2013
RF mixers are workhorses of many RF/wireless designs. There are a number of types in use. Many are passive ( diodes, CMOS quads, etc) and some are active ( single balanced, doubly balanced). A ubiquitous design is the Gilbert cell mixer. It is doubly balanced, provides gain, can be implemented simply in ICs. However, when it comes to low voltage operation it causes issues. Therefore a number of modified Gilbert cell mixers have been proposed. Among them is the mixer described in a recently released brief by Signal Processing Group Inc. Please access it at http://www.signalpro.biz>engineer's corner. For further details and discussion please contact the author at email@example.com.
Monday, April 22, 2013
For high frequency bipolar design there are two parameters which are important in estimating the device performance. ( In actual fact the fmax of the bipolar device is equally important but is not detailed here). tF, the total forward transit time, is used for modeling the excess charge stored in the transistor when its emitter - base junction is forward biased and its collector to base voltage is VBC = 0.0. It is also needed to calculate the transistor's emitter diffusion capacitance. Typically the tF varies with IC ( the collector current). Values of tF generally range from 0.3 nanosecond to a few or fractions of a picosecond for high frequency devices. fT is the transistors's unity gain bandwidth. fT is defined as the frequency at which the common emitter, zero-load, small signal current gain extrapolates to unity. The roll-off is 6dB/octave. This information should be used to determine the performance required for particular device suitable for design at a particular frequency point. tF and fT are parameters used in models that drive CAD programs. In some programs the user can enter fT or tF directly while in others either fT or tF is converted from either parameter. fT can be measured using a small signal method. In this method the ratio Iout/Iin ( the current gain in a common emitter configuration)is measured for a range of frequencies from DC to the 3 dB point and beyond at a desired bias point. Then fT = product of current gain at DC and the 3dB frequency, i.e B0 X fb. Here B0 is the dc current gain and fb is the 3 dB frequency. Alternatively, another B and frequency value can be measured to determine fT. For example, at any frequency, fm, between 3fb and ft/3, the B value at that frequency Bm, is measured. Then fT = Bm X fm. It is recommended that multiple measurements be made to verify that fm lies in the 6 dB/octave roll-off region. Once fT is known tF can be obtained from it using the formulas described elsewhere in this blog.
Gummel plots are a very useful utility that a bipolar fabrication facility provides or can provide. This is a great utility/tool for the bipolar IC designer. In addition to actual device models and layout rules Gummel plots serve to provide, at a glance the DC performance of a bipolar. The plot itself is a semi-logarithmic plot of the collector current and the base current versus the Vbe of the device. From these plots a number of parameters can be estimated very quickly and can be of inestimable value to the designer. Obviously DC forward gain ( Ic/Ib), is clearly shown, the Vbe of the device at current is available, the common base current gain is available in a straightforward manner and the DC gm can be estimated among other parameters.
Friday, April 5, 2013
Two useful definitions for RF amplifiers are available gain and maximum available gain. Available gain is measured with conjugate match at both input and output ports. Then Available gain = Available power at the output port/Available power from the source. This is the maximum gain obtainable from the amplifier. The maximum available gain ( MAG) is often used as a transistor or FET figure of merit. It is defined as the theoretical power gain of the device with its reverse transfer admittance set to zero. The source and load admittances are conjugately matched. The MAG = Absolute value(yf)**2/4gigo where gi and go are the real parts of the input and output admittances. yf is the forward transfer admittance.
Thursday, April 4, 2013
A common circuit used in most wireless receivers is the RSSI circuit or block. It simply measures or provides an indication of the signal strength being received. It is usually implemented within the receiver chip. The circuitry used for the RSSI appears to be simple but there are a number of issues that must be borne in mind. To begin with, a RSSI circuit can be implemented using the concept of log amplifiers. A really good source of information on these is the Analog Devices website. It may take a bit of searching to find the right article but it is worth it.Also a tutorial article has been already published in these blog posts which may be of some use. However, through experience it has been found ( at SPG) that even if we follow prior art on RSSI design it still takes some doing. Here are a few tips if one is thinking of doing a rssi circuit. ( Of course higher frequencies complicate things even more). (1) Must understand the techniques intuitively. (2) Select a process that can meet the ft/IKF/Hfe/CBC requirements easily. (3)Simulations will take a long time so must be prepared for long simulation times. (4) Bond pad and package parasitics will play a significant role in the performance. So the more accurate these are the better. If package parasitic information is not available then it must be generated ( which is a project in its own right). For more information please access the RSSI design paper in the SPG website located at http://www.signalpro.biz, under engineering pages or contact SPG directly using the contact details provided.
Saturday, March 2, 2013
In a number of cases of simulation of variable time waveforms the PWL format is used in SPICE based circuit simulators. If the statement is really short with only two or three pairs of values it can be input manually by hand. However, if the number of (time, value) pairs is large then a resource is required that can generate the PWL waveform using some kind of CAD program. Signal Processing Group Inc., recently released a related script in C++ that can be used for this task. It consists of an input file generated from a text resource ( in this case a MATLAB file, also included)which has a 1,0 vector of numbers. 1,0 of course representing logic high and logic low. This file can be as long as needed. This file is input into the C++ program which converts the file into a PWL statement for the simulator. To access this program please visit http://www.signalpro.biz and go to "Register for free stuff" The program can be downloaded free of cost through this gateway. The program has been tested using Windows XP.To run it on a different platform may require re-compilation and build.
Voltage references are a ubiquitous function in most analog and analog-digital mixed signal designs. In most cases they need not be excessively tightly specified. A very practical voltage reference with good characteristics is the Brokaw`reference named after its inventor Paul Brokaw. It a versatile reference and quite popular. Recently Signal Processing Group Inc., released a detailed report on the complete design and layout of a Brokaw`reference in BiCMOS. To access this report please visit http://www.signalpro.biz and click on "Register for Free Stuff". The entire report can be downloaded for free.
Tuesday, February 12, 2013
Delta-sigma oversampled systems, particularly A/D converters are very useful circuits. This is specially true now when the semiconductor line widths are decreasing significantly and purely analog converters are becoming hard to design and implement in VLSI technology. A delta - sigma converter is mostly digital with a small amount of analog circuitry. As fine line technology is well suited to digital implementation a delta - sigma converter can be very useful indeed. A brief paper on the delta-signal principle was released by Signal Processing Group Inc. and may be found under the free reports accessed by registering on the SPG website by interested readers. Please visit http://www.signalpro.biz.
Thursday, January 31, 2013
One of the very basic MEMS structures is the cantilever beam. This structure can be used in a variety of applications including RF switching, varactors, switches, capacitors, springs etc. Among the many ways to actuate the operation of a cantilever is electrostatics. In this case a voltage is applied across the movable arm of the beam and a baseplate or reference terminal that resides directly below the beam. To bend the beam and to make contact with the baseplate a pull in voltage is necessary. Once the applied voltage reaches the pull in voltage the beam bends and makes contact with the base plate. When the pull in voltage is removed the spring force of the beam restores it to its original state, as long the elastic limits of the beam are not exceeded. A brief whitepaper on this operation is available to interested parties in the engineering pages of Signal Processing Group Inc's website located at http://www.signalpro.biz.
Saturday, January 19, 2013
In Integrated Circuit design and MMIC design, integrated planar inductors are used frequently. These inductors have typically lower quality factors. However, in a variety of applications planar inductors can be used effectively. The simplest planar inductor is a length of high characteristic impedance microstrip line. A brief paper published by Signal Processing Group Inc.,provides design equations for this type of structure. Interested readers can view the paper at SPG's website, http://www.signalpro.biz on the engineering pages web page.
Wednesday, January 2, 2013
Its interesting how the MEMS design development is paralleling the IC design methodology of yesteryear. The process appears to be very similar,only the parameters seem to change. We also see UC Berkeley developing methodology and CAD tools. MIT is also an early entrant into the CAD Tool fray. Commercially available tools from Coventor are available ( for a significant cost) but may be the best deal for the design engineer interested in end results rather than the process. It remains to be seen how this whole industry pans out. However, already there are large numbers of MEMS devices working in commercial systems so the MEMS approach is beginning to make sense. Contact SPG at http://www.signalpro.biz for our experince with MEMS related issues.