Wednesday, December 22, 2010

Analog and mixed signal design: FIR filters

FIR filters are strictly not analog or even mixed signal in nature. They are in fact, digital circuits. However, it seems that more and more of these filters are being used in mixed signal designs, specially in fine line semiconductor processes, where analog processing is used to convert to digital and then circuit blocks such as FIR filters, Comb filters, multipliers etc take on the task of further signal processing within a chip. A perfect example is a sigma delta A/D converter. Here there is a minimum of analog circuitry, followed by significant amounts of digital ciruitry. Among these are digital filters. ( Usually sinc filters). A brief note on the practicalities of FIR filter design are presented and can be found in the engineering pages of the our website:

Monday, November 1, 2010

Analog system design: Second order system analysis and design

Second order systems appear frequently in the design of analog systems as well as digital systems. In most cases these types of systems are difficult to understand analytically and designers must resort to simulations and empirical assessments.
Examples of these types of systems ( or circuits) are PLLs, switching power supplies, analog equalizers, mechanical servomechanisms, filters etc. There are some expressions available to do approximate analysis and design before resorting to long simulations or empirical data gathering. These are mainly based on the second order characteristic equation. Solution of this equation yields at least two very useful quantities. The natural damped frequency and the damping ratio. Use of these parameters can greatly facilitate the analysis and design of second order systems. For a brief cookbook style treatment of this analysis please read the article in our website under engineering pages.

Sunday, October 24, 2010

Cable modeling for high speed data communications

I have not been blogging for a while. The reasons are many, but mostly because of some interesting work that came up. This post is a result of grappling with cable modeling and cable parameter information extraction. The simple comment is, that this is a very tedious affair as very little data is available in the literature. High speed data communication cables come in various disguises. Some of the more popular types are the CATX types and STP ( shielded twisted pair) types. Various gauges are being used. We looked at 24 and 26 AWG types.

The issue is, that if you are designing a cable equalizer for example, you need a cable model. There are a number of ways to do this. The most expensive way is to either buy or rent a laboratory piece of equipment which can perform up to at least 12 Ghz, buy or make connectors, and then make measurements. The other way is to use information available in the literature to build a cable model. The latter is very sparse and difficult to obtain. Anyway both approaches should be tried.

The modeling parameter W in some SPICE based programs is a useful one and with proper manipulation can yield fairly accurate models. It is quite complicated to understand. Simple transmission line models in PSPICE can be used but will only offer very basic models and may not be accurate for design.

There are also cable model ( analytical) parameters available in some text books for coaxial, parallel wire cables, microstrip etc. which can also be used. These can be used to obtain the so-called RLGC SPICE model. Using the RLGC circuit is not enough to model transient response since the cable delay cannot be modeled. A transmission line model is required for this. These too are only first order estimates.

So what is required is more empirical data of cables and cable models. One or two researchers have actually done this. However, the need to model parameters such as attenuation, crosstalk, ISI etc is still an open field, ready for someone to step in and do the needful!

Saturday, June 26, 2010

High speed digital data communications demand

It appears to the author, that the high speed data communications sector of the market is growing fast. At least this is the conclusion that we must draw from the demands on our design resources from various customers.

USB3, 10G, HDMI, etc are all very demanding in terms of the semiconductor processes to be used ( cost effectively ), design techniques, systems engineering, CAD tools, availability of parameterics of cables, connectors, PCB based information and ultimately design techniques to stitch all of these together into a device or subsystem that will actually work in the real world.

As we work through these designs, we find that there is a vast gap between theory and reality. This includes simulations also. This has always been true in some degree with other technologies but in the case of these designs it becomes critical. Designing the devices to operate robustly in the real world is very time consuming and in many ways an art, rather than a science. Design experience is called for more than anything to implement these techniques from an intuitive point of view. We believe this is going to be a most interesting and challenging series of designs. More as the work proceeds.

A low power crystal oscillator at 32,768 Hz

The frequency 32, 768 Hz, is one of the most popular frequencies for crystal oscillators as it is used in most time keeping applications. With the proper interface circuit ( PLLs ) it can also be used for high frequency synthesizers. The actual quartz is also relatively inexpensive and this lends itself to cost effective frequency circuits and timekeeping. Of course temperature control can aso be used to generate TCXOs.

In any case, we recently designed, fabricated and throroughly analyzed a low power crystal oscillator ( in conjunction with our sister company). The circuit was first pass functional. The crystal oscillator section dissipates a mere 200 - 500 nA of current at the rated frequency.

The entire chip consists of a crystal oscillator, a low power analog buffer, a level converter and a digital output buffer capable of driving 100 pF. In addition the device has a means of trimming the frequency using an analog trim as well as a digital fine trim.

The device was evaluated thoroughly and its temperature characteristics measured extensively. Interested parties may contact us through our website at for our experience and these results. All in all a most satisfying experience!

A new silicon proven Rf device - a first pass success!

A first pass success is always welcome. When the sucess is a high frequency device it is doubly so. The latest addition to the high frequency, silicon proven ASSP portfolio, is a high frequency, wideband amplifer fabricated in a 0.35um SiGe process.

It is fairly general purpose and can be used as gain block, an LNA etc. The basic features are as follows:


Usable frequency gain = 100 to > 2500 Mhz
19 dB typical ac gain at 900 Mhz, VCC = 2.7V
NFMIN = 1.2 dB at 900 Mhz
NFMIN = 1.5 dB at 2500 Mhz
1 dB compression point at 900 Mz = 2.9 dBm
1 dB compression point at 2500 Mz = 0.9 dBm
OIP3 at 1.5 Ghz = 15.0 dBm
OIP3 at 2.5 Ghz = 10.0 dBm
Power supply from 2.7 to 5.0 Volt
Power supply current typical = 4.7 mA
Reverse isolation s12 = -48.0 dB min.

The device was tested from -55 Degrees C to 125 Degrees C. An extended frequency test was also done at 5.0 Ghz. The gain dropped to 17 dB. Other parameters were also slightly affected.

Anyone with interest in this device and its development may contact the author via the website located at

Monday, May 31, 2010

Change of menu item "Engineering pages"

The menu item in the website ( has been changed from "Engineering Pages" to " Engineer's corner".

More on the inverted F antenna analysis

An analysis of the printed inverted F antenna was carried out using the NEC2 program. This program is available in the public domain. It models antennas as wires.
One can set the wire radius. The disadvantage of the program is its inability to model dielectrics as substrates. However, in spite of this, with a bit of smarts a lot of information about antennas can be obtained from it. In case of a printed strip, Balanis's book provides the conversion between the wire radius and the width of the strip for those who may be interested in further analysis. Our experience has been that no matter how much modeling is done ( as we did follow up with ADS MOMENTUM)in the end the antenna ends up being tuned by somewhat of a trial and error method. In our opinion both procedures are important. We need a quick way to assess the antenna operation using a program like NEC2 which is surprising fast and a more refined means of simulation like ADS or FEKO. Check out the article in the SPG website ( under engineer's corner for printed antennas. ( Note: "Engineering pages"
has now been changed to "Engineer's corner".

Tuesday, April 20, 2010

The printed inverted F antenna

The printed inverted F antenna ( as opposed to the planar inverted F antenna) is a useful antenna capable of being printed right on the PCB of a wireless product. In an attempt to understand this antenna in more depth, the technical staff of SPG researched the topic. The result was that, there seems to be almost no information on this type of antenna in any of the typical texts on antennas. The only viable source for information on this antenna is the web. This too, is fairly sketchy. Our technical staff has now prepared a white paper containing the type of information on this antenna needed by practising engineers, and will be releasing it shortly via this blog, and in the engineering pages of the website at

Monday, April 12, 2010

Noise figure versus input referred noise

If we use the specification for a low noise amplifier, invariably the noise performance is a Noise Figure. However, in a particular system design we calculated the input referred voltage that could be a limiting factor for the very first stage LNA. The issue was how to convert from the noise figure of a selected LNA ( from Analog Devices no less) to the input referred noise voltage to make sure the amplifier was being chosen correctly. Well here is the conversion at least in one form.

Note: The noise factor is simply 1 + NA/Ni. Ni is the noise power coming in from a 50 Ohm matched source and is equal to -174 dBm/Hz. ( Pretty standard usage).

The noise voltage being generated by the 50 Ohm source is vni=4.46E-8 Vrms/Hz. This can then be used to compare whether the amplifer will work with a particular noise figure ( from the expression 1 + NA/Ni).

Check and see if the number NA, the noise input referred power generated by the amplifier itself, converted from a voltage to power is acceptable or not. Must remember to use the impedance level of 50 Ohm. Simple?

Example: If the NF is = 0.8, then 1+ NA/Ni = 10**0.08 = 1.2 ( approx). We can calculate vna as above for vni.

Here is a note on input noise. It has been found that the -174 dBm/Hz should be modified to -162 dBm/Hz for the rural environment in the US and to -98 dBm/Hz for the urban environment. The -174 dBm/Hz is therefore a theoretical figure used to specify and calculate noise figures and noise factors!

Yes, another thought; we need to make sure that the derivation for the noise factor is elaborated: Here it is:

Noise factor F = SNRi/SNRo where i stands for input and o stands for output.

So = Si X G ( G = Gain)
No = [Ni noise power from the 50 Ohm source + NA, noise power generated by the amp].

F = [Si/Ni] / [GSi/G(Ni+NA)] = 1 + NA/Ni.

Also for other items of engineering interest go to our website at

Saturday, March 20, 2010

Thermal modeling and analysis of devices and MCMs

Thermal modeling and analysis of devices and MCMs ( modules) is becoming very important in recent times. In years past, most of the thermal effort was based on the design of devices, and thermal analysis was built into the circuit simulators such as SPICE. The rest of the modeling based on the electrical analogs of heat transfer was well understood, and could be done in a fairly simple way. Today the situation is quite complex. As more and more performance is demanded from semiconductors ( individually ) and from MCMs ( multi-chip modules ), and indeed entire products, such as cell phones, the heat per area is rising towards the 500 W/cm squared limit. This is a lot of heat, and it is very difficult to use the old methods to model and understand these problems. Therefore thermal modeling is attacking these issues in electrothermal dynamics by using newer CAD tools based on FEM ( Finite element methods ) and CFD ( Computational Fluid Dynamics). A number of new thermal modeling tools have appeared on the market. Some are reasonably priced and others are not. Again you get what you pay for! Heat flow is based on the conduction, convection and radiation of heat ultimately. Thermal CAD tools model these processes in their own proprietary way. We have used a couple of these tools and find them fairly, ( and I mean fairly ) complex. So practice is neccessary. However, the results obtained are within the 20% error band. The accuracy of results also depend on the skill of the user! More on this topic as time goes on. It is a fascinating subject.

Sunday, February 7, 2010

RF/MW ESD and complex matching using resonance

An interesting technique that finds extensive use in RF/MW ESD circuits and complex matching circuits is the concept of resonating out reactances. Taking the case of the ESD circuit we find that in the most usual case RF/MW ESD circuits ( as other ESD circuits do) use some form of diodes to protect sensitive inputs on an IC. This of course leads to a parasitic capacitance which causes loading and mismatches. In order to eliminate the effect of this capacitance, at a single frequency an inductor can be used in parallel with the parasitic capacitance. The value of the inductor is chosen to resonate with the parasitic capacitor and therefore at the resonant frequency the pair becomes invisible leaving only the resistive part to be matched or considered. This is a simple technique which finds wide application in a number of critical circuits. Obviously the limitation is the single frequency characteristic. However, with some subtle manipulations it can also be used in wider bandwidth applications.

Saturday, February 6, 2010

Receiver spurious response rejection

This is a very interesting specification for which no clear definition seems to exist. Note definition 1.0: Spurious rejection is the ratio of a particular out of band frequency signal level required to produce a specified output to the desired signal level to produce the same output. Definition 2.0: " All superheterodyne receivers have a potential for responding to frequencies other than the desired frequency channel. This needs to be minimized by designing in spurious response rejection by proper choice of the IF frequency and use of RF filters. 70 to 100 dB is achieveable in practical receivers." Definition 3.0: Ratio of desired signal to the total of all spurious signals at an offset of channel spacing in dB. What are these spurious responses being considered? A sample of these signals is described below:
(1) Image frequency/ frequencies.
(2) Half - IF.
(3) Straight IF pickup.
(4) High order spurs result from combinations of harmonics ( m,n) which result in spurious responses so close to the desired frequency response that they cannot be filtered out.
(5) A whole family of spurious responses of type ( 1 x n) is the n x LO spurs which can be troublesome if the RF front end has return responses or re-resonances.
(6) Second image in dual conversion receivers.
(7) Spurious signals present on the LO signal itself.
(8) Transmitted signal in half duplex radios assuming the role of a LO.

These responses are difficult to measure because of signal generator wideband noise.

Nevertheless this is a key receiver specification, and needs to be understood and above all, used and specified clearly.

Impedance matching using two useful techniques

For maximum transfer of power from a source to a load, the source and load impedances must be conjugate matched. A number of techniques to do this have been developed. This post looks at two fairly simple and very popular ones. The L - section match and the cascade transmission line match. Simple analytical techniques are used to do this and described in the paper. The calculations can be done with a simple calculator. In order to access the detailed description, interested readers are directed to our website at Follow the links in the website to engineering pages>engineer's corner and then select the paper from the list on the page.

Saturday, January 23, 2010

SFDR or Spurious free dynamic range

Someone asked a question about the significance of the SFDR. The answer to the question was as follows. ( For experienced receiver designers this is old hat of course.)

The SFDR is a specification which allows a reviewer to gauge the range of input/output signals that a receiver can handle while still in a linear range of operation.

The basic mathematical definition is:

SFDR = (2/3) x (IP3 - Noise floor)

The noise floor is defined as:

Pn(output) = kTBGF.

Where k = Boltzman's constant
T = Absolute temperature
IP3 = Third order intercept point at the output
G = Gain of the system
F = Noise factor.

Using this definition the SFDR can be calculated as:

SFDR = (2/3)(IP3 + 174 - 10logB - G - F).

Here the 174 represents the kT noise.

All quantities in dBm.

Thus if IP3 is known and gain is known , the input IP3 is known. The input signal should not exceed this as 3rd order distortion products will emerge from noise beyond this level at the input.

So an obvious conclusion is: Keep IP3 as high as possible and the noise floor as low as possible for high SFDR. Typically IP3 is about 11.6 dB above the 1 dB compression point of an amplifier.

Also it must be stressed that all components in a system, that have the potential of introducing distortion, should be assigned an IP3. Ultimately the final IP3 is the cascade of the individual IP3's.