Learning from failures

This year SPG will be over 24 years old. We have had a long history of projects, most of which were great successes. A few of them spectacular failures. After much soul searching we decided to publish what we think were some outstanding reasons for the failures. As is understandable and usual there were shortcomings and challenges on both sides. SPG and the customer. This post tries to list these and should be read with respect to one of the earliest posts about first pass success, already published in this blog. The reason for this baring of skeletons is to help establish a better and better methodology for success and to avoid mistakes of the past. It may be slightly controversial but its veracity is unquestionable.


Project # 1.0 ( Non - chip project)
1.0 Communication problems. Customer and SPG not communicating comfortably and well.
2.0 No statement of work. No plan. No list of things to do and a timeline associated with it.
3.0 No clear guidance from the customer.
4.0 Bad, bad, bad documentation from the customer. Bits and pieces strung together in random order. Failure of SPG to not accept this.
5.0 Micro – managing by the customer instead of managing.
6.0 Too much anxiety on the customer’s part about the project.
7.0 No specification.

Project #2
1.0 Change of specifications and mission creep.
2.0 Failure to do full chip simulations.
3.0 Initial time estimates were off. Too aggressive a schedule.
4.0 Delay in implementation. Faults on both sides.

Project #3
1.0 Change of specifications. Mission creep.
2.0 Customer pushing to get the database out too quickly before checking got done.
3.0 Severe micro-management by customer..
4.0 Did not correct DRC or LVS problems completely because of 2.0
5.0 Lack of pcb expertise on the customers part.
6.0 Would not let us do the reference pcb design and initial test.

Project #4
1.0 Lack of right design tools and training to use them
2.0 Lack of good communication and comfortable give and take between the two parties.
3.0 Lack of appropriate effort on the project.

Project #5

1.0 Lack of the right process technology.
2.0 Used a process that did not have comfortable performance margins.
3.0 Circuit failure under stress conditions.