Quick turn analog ICs with low risk : The SPG Fastchip technique

It is not unusual that the trio of risk factors: cost, timeline and performance are the inhibitors of analog and mixed ASIC usage. Techniques that can lower these risks can and should be used. The lowest order of risk reduction techniques is breadboarding. Using discrete devices to verify a circuit. However, there are a number drawbacks to this. First of all, a breadboard has higher parasitics ( capacitance, inductance and resistance) and when the design is transferred to an ASIC, performance may not match that obtained on a breadboard. Secondly it is not always that one can get discrete devices which are appropriate for the ASIC design. There are other factors of minor importance that also affect the mapping of a breadboard design to an ASIC. What is needed is a method to cheaply and quickly check out either part or all of a envisaged ASIC cheaply. The SPG Fastchip technique is one approach that is available from Signal Processing Group Inc. Its description may be found under "Engineer's corner" in our website at: http://www.signalpro.biz.