Analog and mixed signal design: A reduced power capacitive load CMOS clock driver

When designing clock drivers for capacitive loads ( or indeed for any load), using a CMOS inverter type driver, the power dissipation can be large if precautions are not taken to attenuate the direct current that flows from the P or N channel output transistors, when, for a fraction of the drive cycle both the transistors may be momentarily ON.

A simple way to alleviate this problem is to use a non - overlapping clock driver. Such a driver is presented on our website at www.signalpro.biz/engineer's corner.
A simple and useful circuit.

Half IF spurious response and the second order intercept point

An irksome 2nd-order spurious response called the half-IF (1/2 IF) spurious response, is defined for the mixer indices of (m = 2, n = -2) for low-side injection and (m = -2, n = 2) for high-side injection. For low-side injection, the input frequency that creates the half-IF spurious response is located below the desired RF frequency by an amount fIF/2 from the desired RF input frequency. The desired RF frequency is represented by 2400 MHz, and in combination with the LO frequency of 2200 MHz, the resulting IF frequency is 200MHz. For this example, the undesired signal at 2300 MHz causes a half-IF spurious product at 200MHz. For high-side injection, the input frequency that creates the half-IF spurious response is located above (by fIF/2) the desired RF. Note that high side injection implies that the LO frequency is above the RF frequency and low side injection implies that the LO frequency is below the RF frequency.

The second order intercept point is used to predict the mixer performance with respect to the half IF spurious response. For further details please see the article under engineer's corner/engineering pages in our website at www.signalpro.biz.

More on cable modeling

In our efforts to understand cable models a little better we took some measured data from Analog Devices ( Analog Dialogue, Vol 38, July 2004, "An adjustable cable equalizer combines a wideband differential receiver with analog switches", Johnathan Pearson) and an approximate expression provided by David A. Johns and Daniel Essig,( "Integrated circuits for data transmission over twisted pair channels", IEEE Journal of Solid State circuits, March 1997. A little dated but very useful, since this is one paper that actually had something we could get our hands around and use practically.)We used MATLAB to generate the loss characteristics as per David Johns et al's paper and plotted it along with the Analog Devices data. From this it appears that at small cable lengths there is generally good agreement between the two sets of data. As cable lengths increase the correspondence gets worse and worse. If one has to use the approximate expression, then a correction factor of from 2.5dB to 7.5dB may be needed to get closer estimates using the theoretical approximate expression. The results are in the "Engineer's Corner" on our website at www.signapro.biz.

Bandwidth requirement to pass fast rising digital signals

How wide must the bandwidth be to pass a fast rising digital pulse so that at the output it can still be recognized as a pulse and detected? A common enough question. However sometimes the answer is not so obvious. Common wisdom says a minimum 3dB point of the filter or medium through which the pulse has to transition must be at least 1/pi*tr where tr is the risetime and pi is 3.1415 etc. Upon simulation using a simple RC filter, the result is: (a) The rule is correct. (b) The pulse width and period must be such as to accomodate the rise and fall time of the pulse. (c) The bandwidth may be narrower if the detection threshold can be set higher. (d) If the detection threshold is low then detection errors may occur if the above rules are disobeyed!

Cable model for high speed data transmission

Looking at cable models, an interesting expression was found. Though approximate and using " typical cable parameters" it can be used to at least get a feel for the challenges of transmitting high speed data down a UTP cable. The expression is: f3db = 2.25E4/(d*d). Here d is the length of the cable in Km. From this an interesting conclusion can be drawn. The bandwidth of this "typical" cable of length 100 Meters is only 2.25 Mhz. At the other extreme, a 1 Meter cable will have a 22.5 GHz of bandwidth. A 10 Meter cable will have a bandwidth of 225 Mhz and so on. So if we need to transmit data at high MHz or low GHz speeds, on a longer cable, then there is no option except to design and use an equalizer. This is of course a whole new ball game with many issues. From an initial assessment it appears that an analog equalizer is the best option here. The design is understandable and the technology is available to implement it in a reasonable amount of cost, time and space on an ASIC as needed.

Analog and wireless design: Re - visiting average and effective values, voltage, current and power.

Having become accustomed to clicking icons on a simulator to get fast readings of average and rms values, power values etc we were startled to find that we could not easily compute effective and/or average values of arbitrary waveforms to crosscheck simulation results. So we decided it was time to re-visit the so called " text book " definitions and see what we come up with and re-educate ourselves. It is often the bare essentials that seem to trip us up sometimes. So after a fairly close look we documented, in a workbook fashion, our findings, just in case we need them from time to time. This little report is available on our website under engineer's corner/engineering pages. For interested readers it is located at www.signalpro.biz.

Analog and mixed signal IC design: DMOS transistors

We are all familiar with the MOSFET. Some of us are also very familiar with JFETs.
However, there are a number of transistor types that are not so common. One of these is the DMOS transistor or double diffused MOS transistor. In recent years the DMOS transistor has been used more and more to provide high voltage capability to analog and mixed signal IC designers. It is very popular in the design of MEMs interfaces where higher voltages are required. Currents are usually not high. DMOS transistors can deliver higher currents but need a larger size. The tradeoff is obvious. The DMOS structure is an interesting one. For further detailed information please go to our website, www.signalpro.biz and take a look at the DMOS tutorial article in the engineering pages.